Why are vias bad for high-frequency PCBs (Printed Circuit Boards)?
Question
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Answer ( 1 )
The frequency of circuit board signals is getting higher and higher. When considering impedance design, the inductance and capacitance of line via parasitics can easily cause impedance discontinuities.
Z = R + j (2πfL-1 / 2πfC)
When using a high-frequency circuit board, the frequency f increases, and we must find ways to reduce the parasitic L and C.
The via includes the thickness of the dielectric layer, that is, the dielectric constant £, the height of the hole h (the height of the via is equal to the height of the PCB), the diameter of the holed, the diameter of the pad D1, and the diameter of the solder mask D2, respectively.
Parasitic capacitance formula: C = 1.41 * £ * h * D1 / (D2-D1)
Parasitic inductance formula: L = 5.08 * h * [ln (4h / d) +1]
How to reduce parasitic capacitance?
1. Select a board with a small dielectric constant
2. Make a thin circuit board
3. Increase solder mask area; copper is a little farther from the pad
Reduce parasitic inductance by choosing a thin PCB
PCB Factory Actual Case
PCB dielectric constant: 4.4
PCB thickness: 50mil
Solder mask diameter: 40mil
Hole pad: 20mil
Aperture: 10mil
Parasitic capacitance 0.3pf, parasitic inductance 1.01nH
The original signal Tr = 1ns, the capacitance causes a rise time change of 19ps, and the inductance causes a 3.2-ohm impedance change.
To summarize the high-frequency circuit board and reduce the capacitance inductance of the via, consider:
–Best method: No vias for high-frequency signal lines
–The second method: parallel vias to reduce equivalent inductance
–If the first two cannot be operated, you can choose the following measures:
1. Use a board with a smaller dielectric constant
2.PCB is thinner
3.Increase solder mask area